1. Field of the Disclosure
The present disclosure relates generally to static random access memory (SRAM) arrays and, more particularly, to test structures for characterizing SRAM arrays.
2. Description of the Related Art
A two-step process is used to read information in a bit cell of a conventional static random access memory (SRAM) array: (1) the bit line (BL) and the complementary bit line (BL) are both pre-charged to a logical high value indicated by “1” and (2) the BL or the BL discharges in response to activating the corresponding word line WL so that BL represents the logical value stored in the bit cell and BL represents the inverse of the logical value stored in the bit cell. Current generated during step (1) is referred to as a “pre-charge current” and current generated during step (2) is referred to as a “read current.” Portions of the SRAM array may fail during read operations due to, for example, process variations during fabrication of the SRAM array, degradation or aging of the SRAM array, and the like. Read failures may be caused by soft oxide breakdown, negative bias temperature instabilities, positive bias temperature instabilities, or hot carrier injection effects. Read failures may also be caused by variations in the pre-charge current or the read current, which may be a function of the device drive strength of pass-gates or pull-down transistors in the bit cell. Test structures may therefore be included in the SRAM to mimic the SRAM array and attempt to predict read or write failure mechanisms in the SRAM array. However, conventional test structures do not decouple the contribution of the pre-charge current and the read current to the read failures.